Publications

2019

• Understanding Algebraic Rewriting for Arithmetic Circuit Verification: a Bit-Flow Model (to appear)
  Maciej Ciesielski, Tiankai Su, Atif Yasin, Cunxi Yu
  IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)

• LAMDA: Learning-Assisted Multi-Stage Autotuning for FPGA Design Closure [Talk]
  Ecenur Ustun, Shaojie Xiang, Jinny Gui, Cunxi Yu, and Zhiru Zhang.
  IEEE Symp. on Field Programmable Custom Computing Machines (FCCM), 2019.

• Painting on Placement: Forecasting Routing Congestion using Conditional Generative Adversarial Nets (to appear) [GIF Link]
  Cunxi Yu, Zhiru Zhang
  ACM/IEEE Design Automation Conference (DAC'19)

• Spectral Approach to Verifying Non-linear Arithmetic Circuits [Algebraic Spectrum Gallery & Github]
  Cunxi Yu, Atif Yasin, Tiankai Su and Maciej Ciesielski
  ACM/IEEE Asia and South Pacific Design Automation Conference (ASP-DAC'19)

• Performance Estimation of Synthesis Flows cross Technologies using LSTMs and Transfer Learning
  Cunxi Yu, Wang Zhou
  arXiv preprint:1811.06017 [cs.LG]

• Algorithmic Obfuscation over GF($2^m$)
  Cunxi Yu, Daniel Holcomb
  arXiv preprint:1809.06207 [cs.CR]

2018

• Rewriting Environment for Arithmetic Circuit Verification [Github]
  Cunxi Yu, Atif Yasin, Tiankai Su, Alan Mishchenko and Maciej Ciesielski
  International Conference on Logic Programming and Automated Reasoning (LPAR-22) vol 57, pages 656--666.2019

• Developing Synthesis Flows without Human Knowledge [Datasets & Demo @Github]
  Cunxi Yu, Houping Xiao and Giovanni De Micheli
  ACM/IEEE Design Automation Conference (DAC'18)

• End-to-End Industrial Study of Retiming
  Cunxi Yu, Chau-Chin Huang, Gi-Joon Nam, Mihir Choudhury, Victor N. Kravets, Andrew Sullivan, Maciej Ciesielski, Giovanni De Micheli
  2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI'18)

• Generating Safety Guidance for Medical Injection with Three-Compartment Pharmacokinetics Model
  Cunxi Yu, Heinz Riener, Francesca Stradolini, Giovanni De Micheli
  2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI'18)

• Formal Analysis of Galois Field Arithmetic - Parallel Verification and Reverse Engineering [Github] [Benchmarks] [arXiv]
  Cunxi Yu, Maciej Ciesielski
  IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. (TCAD'18) 10.1109/TCAD.2018.2808457

• Fast Algebraic Rewriting based on And-Inv-Graphs [Github]
  Cunxi Yu, Maciej Ciesielski and Alan Mishchenko
  IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. (TCAD'18) 10.1109/TCAD.2017.2772854

• Survey on applications of formal methods in reverse engineering and intellectual property protection
  Shahrzad Keshavarz, Cunxi Yu, Samaneh Ghandali, Xiaolin Xu, Daniel Holcomb
  2018 Journal of Hardware and Systems Security (HaSS'18)

• Computer Algebraic Approach to Verification and Debugging of Galois Field Multipliers
  Tiankai Su, Atif Yasin, Cunxi Yu, Maciej Ciesielski
  IEEE International Symposium on Circuits and System (ISCAS'18) IEEE, May 2018

2017

• Advanced Datapath Synthesis using Graph Isomorphism
  Cunxi Yu, Mihir Choudhury, Andrew Sullivan and Maciej Ciesielski
  2017 International Conference On Computer Aided Design (ICCAD'17), Nov. 13 - 16, 2017, Irvine, CA, USA.

• Formal Verification of Truncated Multipliers using Algebraic Approach
  Tiankai Su, Cunxi Yu, Atif Yasin, and Maciej Ciesielski
  2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI'17), July 3-5, 2017, Bochum, Germany

• Advanced Logic synthesis of Datapaths using Graph Isomorphism
  Cunxi Yu, Mihir Choudhury, David Geiger, Andrew Sullivan and Maciej Ciesielski
  IWLS 2017, June 2016, Austin, USA.

• Reverse Engineering Irreducible Polynomial of GF(2^m) Arithmetic (Benchmarks)
  Cunxi Yu, Daniel Holcomb and Maciej Ciesielski
  IEEE/ACM/EDAA Design, Automation and Test in Europe (DATE'17), March 2017. Lausanne, Switzerland

• Efficient Parallel Verification of Galois Field Multipliers. (Best Paper Nomination) (Benchmarks)
  Cunxi Yu and Maciej Ciesielski
  IEEE/ACM 22nd Asia and South Pacific Design Automation Conference (ASP-DAC'17), Jan. 16-19, Chiba/Tokyo, Japan.

2016

• Formal Verification of Arithmetic Circuits by Function Extraction. [Tool] [Benchmarks](Best Paper Nomination)
  Cunxi Yu, Walter Brown, Duo Liu, Andre Rossi , Maciej Ciesielski.
  IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. (TCAD'16) 10.1109/TCAD.2016.2547898

• Incremental SAT-based Reverse Engineering of Camouflaged Logic Circuits. [Project Web] [Source code] [Benchmarks]
  Cunxi Yu, Xiangyu Zhang, Duo Liu, Maciej Ciesielski, Daniel Holcomb.
  IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. (TCAD'16)

• Formal Verification using Don’t-care and Vanishing Polynomials.
  Cunxi Yu and Maciej Ciesielski
  2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI'16) , July 2016, Pittsburgh, PA, USA

• Analyzing Imprecise Adders using BDDs - A Case Study.
  Cunxi Yu and Maciej Ciesielski
  2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI'16) , July 2016, Pittsburgh, PA, USA

• DAG-Aware Logic synthesis of Datapaths (Corrected version).
  Cunxi Yu, Mihir Choudhury, Andrew Sullivan and Maciej Ciesielski
  IEEE/ACM 53rd Design Automation Conference (DAC'16), June 2016, Austin, USA.

• Automatic Word-level Abstraction on Datapaths.
  Cunxi Yu and Maciej Ciesielski
  IEEE International Symposium on Circuits and System (ISCAS'16) IEEE, May 2016, Montreal, Canada.

• Oracle-Guided Incremental SAT Solving to Reverse Engineer Camouflaged Logic Circuits.
  Duo Liu, Cunxi Yu and Daniel Holcomb
  IEEE/ACM/EDAA Design, Automation and Test in Europe (DATE'16), March 2016, Dresden, Germany.

2015

• Logic Debugging of Arithmetic Circuits.
  Samaneh Ghandali, Cunxi Yu, Duo Liu, Maciej Ciesielski
  2015 IEEE Computer Society Annual Symposium on VLSI (ISVLSI'15) , July 2015, Montpellier, France.

• Verification of Arithmetic Datapath Designs using Word-level Approach.
  Cunxi Yu, Walter. Brown and Maciej. Ciesielski
  2015 IEEE International Symposium on Circuits and Systems (ISCAS). May 2015, Lisbon,Portugal.

• Verification of Gate-level Arithmetic Circuits by Function Extraction[Tools + Benchmarks]
  Maciej Ciesielski, Cunxi Yu, Walter Brown, Duo Liu and Andre Rossi
  IEEE/ACM 52nd Design Automation Conference (DAC). June, 2015, San Francisco, CA, USA.

• Diagnosis and Debugging of Arithmetic Circuits
  Samaneh Ghandali, Cunxi Yu, Duo Liu, Maciej Ciesielski
  IEEE/ACM 52nd Design Automation Conference (DAC-WIP). June, 2015, San Francisco, CA, USA.

• Verification of Sequential Arithmetic Circuit.
  Cunxi Yu, Duo Liu, Walter Brown, Samaneh Ghandali, Maciej Ciesielski
  IEEE/ACM 52nd Design Automation Conference (DAC-WIP). June, 2015, San Francisco, CA, USA.

Teaching

• Teaching Assistant, ECE 667 (Grad) - Synthesis and Verification of Digital Systems (Spring 2016), UMass Amherst.

• Teaching Assistant, ECE 597/697 (Grad) - Embedded System (Spring 2015), UMass Amherst

• Teaching Assistant, ECE 221 (Undergrad) - Introduction to Digital Systems(Fall 2015), UMass Amherst

   

Awards

• Winner of The DAC 2017 Hardware Security Contest (Hack@DAC'17) - 1st Place

• 2017 IWLS Travel Grant

• 2017 ASP-DAC Best paper nomination

• 2016 IEEE TVLSI Travel Grant

Professional Service

• Organization: ASAP'19

• TPC Member: IWLS'17, IWLS'18, IWLS'19, DUHDe@DATE'19, ASP-DAC'20

• Conference Reviewer: VTS'15, ICCAD'15, CHES'16, DAC'17, DAC'18, ASPDAC'19, FPGA'19

• Journal Reviewer: IEEE Transactions on VLSI, IEEE Design&Test, IEEE Transactions on CAD, IEEE Transactions on Information Forensics and Security

Presentations

• Painting on Placement: Forecasting Routing Congestion using Conditional Generative Adversarial Nets. Design Automation Conference (DAC'19). June 2019.

• Approaching The Age of Autonomous IC Design System. Cornell, UMass, UoUtah. Spring 2019

• Developing Synthesis Flows without Human Knowledge. ACM/IEEE Design Automation Conference (DAC'18). CA, USA. June 2018

• Approaching Human-Free Synthesis Synthesis for IC Design. Technische Universität Kaiserslautern. June 2018.

• Approaching Human-Free Synthesis Synthesis for IC Design. IBM T.J. Watson Research Center. March. 2018

• Advanced Datapath Synthesis using Graph Isomorphism. ICCAD 2017, Irvine, CA, USA, November 2017.

• Reverse Engineering Irreducible Polynomial of GF(2^m) Arithmetic. DATE'2017, Lausanne, Switzerland, March 2017.

• Efficient Parallel Verification of Galois Field Multipliers. ASP-DAC'17, Japan, Tokyo/Chiba.

• Computer Algebra Knows Arithmetic Better. École polytechnique fédérale de Lausanne (EPFL). December 2016. Lausanne, Switzerland

• Formal Analysis of Arithmetic Circuits using Computer Algebra Method. Cadence Conformal LEC. September 2016, Cadence, San Jose, CA, USA.

• Advanced Datapath Synthesis using Graph Isomorphism. IBM CMOS Design Forum. September 2016, IBM T.J Watson Research Center, Yorktown Height, NY, USA

• Formal Verification using Don’t-care and Vanishing Polynomials. 2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI’16) , July 2016, Pittsburgh USA.

• Analyzing Imprecise Adders using BDDs - A Case Study. 2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI’16) , July 2016, Pittsburgh USA

• DAG-Aware Logic synthesis of Datapaths. 53rd Design Automation Conference (DAC’16), June 2016, Austin, USA.

• Automatic Word-level Abstraction on Datapaths. 2016 IEEE International Symposium on Circuits and System (ISCAS’16) IEEE, May 2016, Montreal

• Logic Minimization of Multiplexers and the Surrounding Logic. IBM CMOS Design Forum. August 2015, Yorktown Height, NY, USA.

• Verification of Gate-level Arithmetic Circuits by Function Extraction. 52nd Design Automation Conference (DAC’15), June 2015, San Francisco, USA.